THE SCHOOL OF MATERIALS SCIENCE AND ENGINEERING   

GEORGIA INSTITUTE OF TECHNOLOGY     

Under the provisions of the regulations for the degree 
   

DOCTOR OF PHILOSOPHY 
   

on Thursday, April 13, 2023  

9:00 AM  

in person in

Marcus 1117-1118 

  
and virtually via

Microsoft Teams

Click here to join the meeting

Meeting ID: 255 798 080 68
Passcode: yyeXs4

will be held the  

DISSERTATION DEFENSE 
 
for  

Amy C. Brummer

“Engineering a Self-Aligned Metal-Oxide-Semiconductor Gate Stack for Nano-Modular Device Fabrication”

Committee Members:  

Prof. Eric Vogel, Co-Advisor, MSE  

Prof. Michael Filler, Co-Advisor, ChBE  

Prof. Mark Losego, MSE  

Prof. Natalie Stingelin, MSE 

Prof. Asif Khan, ECE  

Abstract:  

Conventional integrated circuit technology has made great strides over the past 50 years and today can produce integrated circuits (ICs) with billions of nanoscale transistors. However, much of today’s state-of-the-art semiconductor research focuses on technological improvements and advancements for manufacturing within the already established IC fabrication framework. The planar process for IC manufacturing involves hundreds of precise processing steps to fabricate monolithic ICs, and the development of new chip designs is an expensive and long process, which can limit process and product innovation. But what if electronics fabrication could be a more dynamic and customizable process that could still manufacture are large scales? By shifting the fabrication paradigm and embracing scalable, bottom-up manufacturing techniques, fully formed high-performance transistors can be produced and interconnected for low-cost fabrication of customizable circuitry. For example, high-performance modular nanowire transistors can be synthesized using bulk processing methods. The pre-fabricated devices can be deposited on a substrate, and metal interconnects can be adaptively printed to form circuits.

This work focuses on developing a self-aligned gate stack that would enable the production of bottom-up nanowire electronic devices and on understanding how material deposition and post-processing impacts performance of the devices. A polymer masking material is used to pattern dopant-modulated silicon (Si) nanowires. This enables the selective deposition of a high-κ dielectric and a metal electrode via atomic layer deposition (ALD) to form a metal-oxide-semiconductor (MOS) gate stack around the channel region of the nanowire. This final structure is a functional, nano-modular field-effect transistor device that can be interconnected with other devices to form circuits.

In the first part of this work, we develop the techniques and investigate the materials needed to fabricate the self-aligned gate stack. The polymer patterning process, referred to as Selective Co-Axial Lithography via Etching of Surfaces (SCALES), has been previously demonstrated by the group on semiconductor nanowires. This works adapts the SCALES process for planar Si substrates to enable the use of characterization techniques that require samples larger than a nanowire. With the planar SCALES process, a polymer film is synthesized across the entire surface of a planar, dopant-modulated substrate and then selectively etched with potassium hydroxide. Polymer remains attached to the heavily boron-doped regions, resulting in a polymer mask aligned to the dopant pattern of the underlying substrate. This patterned polymer mask enables the use of area-selective atomic layer deposition (AS-ALD) to deposit the high-κ dielectric and metal electrode. The selectivity of deposition is investigated for a variety of oxides and metals via AS-ALD, and ultimately hafnium oxide and platinum are determined to be the optimal materials system.

The second part of this work focuses on fabricating and optimizing the self-aligned gate stack. We first demonstrate the successful deposition of a complete MOS gate stack by selectively depositing Pt on top of HfO2 on a boron-patterned Si substrate. The resulting structures are MOS capacitors that are characterized electronically to investigate how the selective deposition and post-deposition anneal impacts device performance. The quality of the oxide-semiconductor interface is particularly important for MOS device performance, so the HfO2-Si interface is investigated in detail by examining different SiO2 interlayer formation techniques. Physical characterization is used to understand the relationship between the interlayer formation and electrical performance. In summary, this work develops a self-aligned gate stack fabrication process and investigates the impact of processing on the electrical performance of the materials. And this self-aligned gate stack deposition process provides a pathway towards fabricating modular nanowire transistors.