Title: Vertical Integration in Open-source Hardware-Software Co-Design for Accelerator Architecture Research
Blaise Tine
Ph.D. Candidate
School of Computer Science
Georgia Institute of Technology
Date: Thursday, July 20
Time: 10:00 AM – 12:00 PM (EDT)
Location: Klaus 2100
Join Zoom Meeting
https://gatech.zoom.us/j/91911412981?pwd=NEJZQnJSYXNNV0ZLY2JUeHYrVk1uQT09
Meeting ID: 919 1141 2981
Passcode: 785293
Committee
Dr. Hyesoon Kim (Advisor) - School of Computer Science, Georgia Institute of Technology
Dr. Krishna Tushar - School of Computer Science, Georgia Institute of Technology
Dr. Sarkar Vivek - School of Computer Science, Georgia Institute of Technology
Dr. Alexandros Daglis - School of Computer Science, Georgia Institute of Technology
Dr. Luca Carloni - School of Computer Science, Columbia University
Thesis
Open-source GPU hardware research is a cross-disciplinary effort in hardware design, compiler, and software development where the trade-off between compatibility, maintenance, integration, and adoption calls for a holistic approach that presents unique challenges and research opportunities at all layers of the infrastructure.
Abstract
The emergence of data-parallel architectures and General-Purpose Graphics Processing Units (GPGPUs) has opened new opportunities to address the power limitations and scalability of multi-core processors, paving the way for novel methods to exploit the abundant data parallelism present in emerging big-data parallel applications, such as graphics rendering, machine learning, and graph analytics. GPGPUs, in particular, with their Single Instruction Multiple Threads (SIMT) execution model, heavily leverage data-parallel multi-threading to maximize throughput at a relatively low energy cost. Over the past decade, GPGPU architecture research has primarily focused on cycle-level simulations that model the hardware architecture at the Intermediate Language (IL) level. Simulating complex hardware at the IL level obscures several aspects of the microarchitecture that significantly impact performance. This dissertation aims to address this research gap, drawing inspiration from the innovations that have occurred in the RISC-V ecosystem and the open-silicon initiative.
In this dissertation, we first propose an Open ISA specification for SIMT-based general-purpose processors, making the case for a minimal extension to RISC-V to support a full-scale GPGPU. We also present a detailed hardware implementation of the propcessor microarchitecture targeting this extension, introducing new microarchitectural building blocks to increase parallelism in the cache subsystem. Another key contribution of this work is the introduction of a discrete hardware pipeline to accelerate graphics rendering, wherein we explore the trade-off between software and fixed-function acceleration. To support this GPU microarchitecture, we propose unique compiler support for control-flow divergence that mitigates our trade-offs for maintaining compatibility with the RISC-V ISA. The second part of this work looks at the software development toolchain to support open hardware, more specifically addressing its main challenges which are the programming interface and simulation. Our framework has been used to instigate several cross-disciplinary research projects both inside and outside the university.