Ph.D. Proposal Oral Exam - Sheng-Chun Kao

Title:  Hardware and Dataflow Optimization for Efficient DNN Accelerators


Dr. Krishna, Advisor     

Dr. Hao, Chair

Dr. Sarkar

Abstract: The objective of this research is to leverage ML techniques to optimize the designflow of the DNN accelerator. Many SOTA DNN accelerator designs still rely on a human-driven design process which costs huge engineering effort for each new generation of DNNaccelerators and becomes increasingly harder to keep up with the innovation speed of DNNmodels.  There is two main focus of accelerator design:  HW resource configuration andmapping where mapping can further be categorized to intra-layer mapping and inter-layermapping.   Finally  in the new trend of multi-accelerator platform  the mapping acrossaccelerator becomes the fourth dimension of the accelerator design. This research target topropose an ML-based solution for each of the four major steps in DNN accelerator design.In this research we present (1) an ML-assisted HW resource allocation method drivenby the RL-based algorithm (2) an automatic intra-layer mapping search tool driven by aGA-based algorithm and finally we plan to develop (3) an ML-based technique to optimizeinter-layer mapping and (4) an ML-based solution to optimize cross-accelerator mapping.These ML-assisted design tools can be used independently to swap out part of the manual-tuning process in the lengthy and engineer-intensive DNN accelerator design process orused simultaneously to reveal a full-fledged ML-assisted DNN accelerator design flow.

Event Details


  • Wednesday, November 10, 2021
    3:00 pm - 5:00 pm

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