Ph.D. Dissertation Defense - Jared Ivey

TitleValidation of Scalable Software-defined Network Simulations using Simulation-based Routing Applications


Dr. George Riley, ECE, Chair , Advisor

Dr. Henry Owen, ECE

Dr. Yorai Wardi, ECE

Dr. Russ Clark, CoC

Dr. Richard Fujimoto, CoC


With farther reaching applications being developed in the realm of software-defined networking (SDN), simulation can justify the feasibility of deploying initial SDN capabilities in a network or assist with troubleshooting and testing existing SDN deployments as a part of maintenance or expansion. This work describes an SDN simulation framework that supports realistic and portable SDN capabilities. Direct Code Execution (DCE) in the network simulator ns-3 is extended to allow the execution of network programs written in Python and Java. Support for CUDA libraries in DCE is provided, permitting the simulation of portable GPU-based network applications. An SDN simulation framework in ns-3 and DCE is designed allowing scalable, portable simulation of SDN controller applications written for the Python-based libraries POX and Ryu supporting OpenFlow 1.0 and 1.3. Similarly to simulation, SDN provides an environment where an entire topology is controlled collectively. The mechanisms that are used to manage routing decisions in simulation can be leveraged for use in SDN. Dynamic, on-demand packet routing in SDN is described that exploits currently existing headers and OpenFlow rules to provide a routing solution influenced by NIx vectors. The use of a parallelized version of the Floyd-Warshall algorithm is studied in the context of SDN as well using the massively parallel processing capability of GPUs. With this effort, route generation for scalable SDN topologies is accomplished in less time than with sequential graph algorithms. The final part of this work aims to provide representative performance profiles that introduce appropriate latencies and other behaviors into the SDN simulation framework. Using multiple Ryu applications, scalable network topologies are tested using both the hardware testbed GENI and network simulations. Controller processing time is gathered and evaluated with the goal of working toward statistically similar results in both environments. A model is designed and evaluated for an adequate representation of instruction processing time distributions in an SDN controller operating in simulation.

Event Details


  • Wednesday, April 26, 2017
    12:00 pm - 2:00 pm
Location: Room 3202, Klaus